A Novel High Computing Power Efficient VLSI Architectures of Three Operand Binary Adders

Two Operand Binary Adders with Threshold Logic

This paper deals with a new method for implementing Binary Adders of two operands whose main characteristics are: They are built using only threshold gates; carry output, besides carry input, is used to obtain each sum bit and the total number of gates is a linear function of the number of bits of the operands (n).

Design of High-Speed Low-Power Parallel-Prefix VLSI Adders

Parallel-prefix adders offer a highly-efficient solution to the binary addition problem. Several parallel-prefix adder topologies have been presented that exhibit various area and delay characteristics. However, no methodology has been reported so far that directly aims to the reduction of switching activity of the carry-computation unit. In this paper by reformulating the carry equations, we i...

High Speed Power Efficient Asynchronous Adders

Fast Signed-Digit Multi-operand Decimal Adders

Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 7542008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are adva...

Theoretical Estimation of Power Consumption in Binary Adders

This paper presents a novel approach for theoretical estimation of power consumption in digital binary adders. Closed-form expressions for power consumption of four different types of binary adders – the ripple-carry adder, the Manchester adder, a multiplexor-based carry-select adder and an efficient tree-based look-ahead adder – are derived in terms of word-length and pre-computed technologysp...